The present disclosure relates generally to scannable and non-scannable latches, and more specifically, to a method, system, and computer program product for initializing scannable and non-scannable latches from a common clock buffer.
Semiconductor chips containing digital logic contain a variety of sequential memory logic elements that are clocked in local synchronous groups by a controllable local clock buffer circuit. The local clock buffer circuit is connected to a global clock grid or clock tree. Different latch types are clocked by different local clock buffers depending on their type. When new latch types are added to a region on the semiconductor chip, the latches are installed along with a local clock buffer circuit. This additional local clock buffer circuit consumes additional power, occupies additional area, and adds additional capacitive load points to the global clock grid or global clock tree.